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Dwarkesh Podcast

Dwarkesh Patel

5 episodes summarised · 5.5h of listening, ~39 min of reading
✨ Summarised by Whipscribe
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What will computer chips look like in 2045?

⏱ 69 min listen · ~2 min read 🎙 Pushkar Ranade

It is a rare look inside a leading-edge chipmaker, with Intel's own engineers and CTO explaining why AI chip supply cannot simply be scaled up.

Key takeaways
  1. 01Dwarkesh Patel toured Intel's fabs and labs for two days, interviewing the engineers bringing up the 18A and 14A processes and Intel's CTO.
  2. 02Intel's backside power moves power lines under the transistors, so one High-NA EUV pass can print 14A wiring that TSMC would need to double-pattern.
  3. 03Pushkar Ranade estimates the world's tools could support about 2x Intel's leading-edge wafer output, not 10x, while AI compute has grown about 3x a year.
  4. 04ASML builds fewer than 100 EUV scanners a year, and Ranade puts tool lead times near 18 months, pushing any new fab capacity toward 2030.
Chapters
0:47 · How Intel tunes the 14A process toward high yield3:54 · Lessons from the delayed 10 nanometer node6:46 · From planar transistors to FinFET and gate-all-around13:11 · Why High-NA EUV pays off for Intel but not TSMC19:19 · Copper, backside power and 3D chips by 204522:42 · Heat as the long-run limit on stacked logic+8 more
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